In an effort to reduce the size of mobile electronic devices and increase the battery life of such devices, an emphasis has been placed on implementing low voltage circuit designs. However, designers of low voltage, nano-scale circuits face many challenges. One such challenge includes the design of reliable low voltage memory circuits. In particular, static random access memory (SRAM) cells can suffer performance degradation at low supply voltages. A typical SRAM memory can have millions of bit cells wherein each bit cell stores one bit of data. At low supply voltages, conventional memory systems cannot always reliably read, write, and retain data.
Operation of a SRAM is influenced by many factors. Specifically, when integrated circuits are manufactured, small variations in doping, layer thicknesses, and other procedures manifest as imprecise threshold voltages, leakage currents, and junction mismatches. These variations can effect operation of a SRAM. The ability of a memory to read and write data is measured in terms of static noise margin (SNM), write margin (WM), and cell current (Icell). The SNM of a SRAM memory cell is generally defined as the minimum noise voltage that, when present at a bit cell storage node, will make a bit cell flip to a wrong state. A bit cell is most vulnerable to noise during a read phase, during which, if a cell changes state a destructive read is said to occur. Cell current is the amount of current the memory cell can source or sink during a read phase. Wherein, write margin can be defined as a minimum voltage required on a bit line to pull a storage node low and flip the state of the bit cell from a high state to a low state during a write phase. A low write margin can lead to unsuccessful writes because it indicates that it is difficult to get data lines to drop to near zero volts. It is well known that design changes that improve one characteristic nearly always degrade at least one of the other characteristics, often to unacceptable levels. Accordingly, there is a need for a SRAM memory cell configuration that can overcome these problems